109 - Bugfixes for CPU emulation correctness and stability. 108 - Updated / fixed instrumentation callbacks. bochsrc so it become possible to 107 emulate 32 - bit CPUs using Bochs binary compiled with x86 - 64 support. ![]() 106 - Now you could disable x86 - 64 from. 105 - Added APIC timer TSC - Deadline mode emulation support. 104 - Added INVPCID instruction emulation support. 103 - Implemented VM Functions support and EPTP - Switching VM Function. 101 - Implemented VMX preemption timer VMEXIT control ( patch by Jianan Hao ) 102 - Implemented Pause - Loop Exiting Secondary VMEXIT control. 99 - Added support for AMD SSE4A / XOP / FMA4 / TBM extensions emulation, the 100 instructions can be enabled using. 98 The BMI instructions support can be enabled using. 97 - Added support for Bit Manipulation Instructions ( BMI1 / BMI2 ) emulation. 96 The FMA instructions support can be enabled using. The implementation 95 was ported ( with few bugfixes ) from QEMU patch by Peter Maydell. 94 - Added support for AVX2 FMA instructions emulation. 92 - Added emulation of AVX float16 convert instructions, the feature can be 93 enabled using. When compiled in, AVX still has to be enabled 91 using. 89 - Added support for AVX and AVX2 instructions emulation, to enable configure 90 with - enable - avx option. 87 - Added support for XSAVEOPT instruction, the instruction can be enabled 88 using. 84 85 - Implemented Supervisor Mode Execution Protection ( SMEP ), the feature can 86 be enabled using. 82 * It is also safe to use large ( up to 16 instructions ) quantum values for 83 the SMP emulation now and improve performance even further. Each emulated processor will execute 81 the whole trace before switching to the next processor. New implementation uses dynamic CPU quantum value and takes 80 full advantage of the trace cache. The 75 feature is enabled by default when configure with - enable - all - optimizations 76 option, to disable handlers chaining speedups configure with 77 - disable - handlers - chaining 78 - New way of CPUs scheduling in SMP mode brings up to 50 % speedup to the 79 SMP emulation. 73 74 - 10 % emulation speedup with handlers chaining optimization implemented. cc ) 20 - fixed compilation err with x86 hw breakpoint enabled and CPU_LEVEL " 72 * Query for supported CPU models using command line option : - help cpu. BASE got corrupted after 10 saving / restoring unusable FS selector 11 - VMX : fixed VirtualBox failures with VMX + EPT enabled 12 - Better report of supported CPUID features when not using pre - defined CPUID profile 13 14 - Debugger / Instrumentation 15 - fixed typo - closing SF bug step all command fails in SMP mode 16 - instrumentation : added special indication for indirect call / jump 17 18 - Configure and compile 19 - fixed compilation err in instrumentation call ( tasking. ![]() 1 ( January 6, 2012 ) : 2 3 - CPU / CPUDB 4 ! Added Athlon64 ( Venice ) configuration to the CPUDB 5 - BMI : fixed EFLAGS after BMI instructions 6 - MSR : access to AMD extended MSR space was impossible due to a bug in RDMSR / WRMSR 7 - VMX : fixed VMFUNC instruction behavior to align with Intel SDM revision 041 8 - VMX : fixed Bochs PANIC when doing I / O access crossing VMX I / O permission bitmaps 9 - VMX : fixed VirtualBox VMX guest Guru Meditation - FS. Large files files are truncated, but you can click here to view the full file 1 Changes in 2.5.
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